DSP56F801PB/d rev. 4.0 , 1/2002 ? motorola, inc., 2002. all rights reserved. dsp56f80 1 product brief dsp56f801 16-bit digital signal processor ? up to 40 mips operation ? dsp and mcu functionality in a unified, c-efficient architecture ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ?8k 16-bit words program flash ?1k 16-bit words program ram ?2k 16-bit words data flash ?1k 16-bit words data ram ?2k 16-bit words bootflash ? hardware do and rep loops ? 6-channel pwm module ? two 4-channel, 12-bit adcs ? serial communications interface (sci) ? serial peripheral interface (spi) ? general purpose quad timer ?jtag/once tm port for debugging ? on-chip relaxation oscillator ? 48-pin lqfp package ?11 shared gpio figure 1. dsp56f801 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit pll clock gen or optional internal relaxation osc. 16-bit dsp56800 core pab pdb xdb2 cgdb xab1 xab2 gpiob3/xtal gpiob2/extal interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset irqa application- specific memory & peripherals interrupt controller program memory 8188 x 16 flash 1024 x 16 sram boot flash 2048 x 16 flash data memory 2048 x 16 flash 1024 x 16 sram cop/ watchdog spi or gpio sci0 or gpio quad timer d or gpio quad timer c a/d1 a/d2 adc 4 2 3 4 4 6 pwm outputs fault input pwma 16 16 vcapc v dd v ss v dda v ssa 6 24 5 vref
2 dsp56f801 product brief motorola dsp56800 digital signal processing core features ? efficient 16-bit dsp56800 family dsp engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/once debug programming interface dsp56f801 memory features ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low cost, high volume flash solution 8k 16 bit words of program flash 1k 16-bit words of program ram 2k 16-bit words of data flash 1k 16-bit words of data ram 2k 16-bit words of bootflash ? programmable bootflash supports customized boot code and field upgrades of stored code through a variety of interfaces (jtag, can, spi) dsp56f801 peripheral circuit features ? pulse width modulator (pwm) with six pwm outputs, two fault inputs, fault-tolerant design with deadtime insertion; supports both center- and edge-aligned modes ? two 12-bit, analog-to-digital converters (adcs), which support two simultaneous conversions with two 4-multiplexed inputs; adc and pwm modules are in sync ? general purpose quad timer: timer d with three pins (or three additional gpio lines) ? serial communication interface (sci) with two pins (or two additional gpio lines) ? serial peripheral interface (spi) with configurable four-pin port (or four additional gpio lines) ? eleven multiplexed general purpose i/o (gpio) pins ? computer-operating properly (cop) watchdog timer ? two dedicated external interrupt pins
motorola dsp56f801 product brief 3 ? external reset pin for hardware reset ? jtag/on-chip emulation (once?) for unobtrusive, processor speed-independent debugging ? software-programmable, phase lock loop-based frequency synthesizer for the dsp core clock ? oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator for lower system cost and two additional gpio lines energy information ? fabricated in high-density cmos with 5v tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available dsp56f801 description the dsp56f801 is a member of the dsp56800 core-based family of digital signal processors (dsps). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the dsp56f801 is well-suited for many applications. the dsp56f801 includes many peripherals that are especially useful for applications such as: motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, automation. the dsp56800 core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. best in class development environment the sdk (software development kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique c application code independent of component architecture. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards will support concurrent engineering. together, the sdk, codewarrior, and evms create a complete, scalable tools solution for easy, fast, and efficient development. product documentation the four documents listed in table 1 are required for a complete description and proper design with the dsp56f801. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/dsp.
DSP56F801PB/d motorola and the stylized m logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. ? motorola, inc. 2002. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1C303C675C2140 or 1C800C441C2447 japan: motorola japan ltd.; sps, technical information center, 3C20C1, minamiCazabu. minatoCku, tokyo 106C8573 japan. 81C3C3440C3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kon g . 852C26668334 technical information center: 1C800C521C6274 home page: http://www.motorola.com/semiconductors/ motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application o r use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical param eters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all oper ating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any licens e under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for sur gical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer s hall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. table 1. dsp56f801 chip documentation ordering information consult a motorola semiconductor sales office or authorized distributor to order parts. topic description order number dsp56800 family manual detailed description of the dsp56800 family architecture, and 16-bit dsp core processor and the instruction set dsp56800fm/d dsp56f801/803/805/807 users manual detailed description of memory, peripherals, and interfaces of the dsp56f801, dsp56f803, dsp56f805, and dsp56f807 dsp56f801-7um/d dsp56f801 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions dsp56f801/d dsp56f801 product brief summary description and block diagram of the dsp56f801 core, memory, peripherals and interfaces (this document) DSP56F801PB/d table 2. dsp56f801 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56f801 3.0C3.6 v plastic quad flat pack (lqfp) 48 80 dsp56f801fa80
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